Net Diagnosis Using Stuck-at and Transition Fault Models by

As deep sub-micron technologies are widely adopted in modern VLSI design and fabrication process, the shrinking size and increasing complexity of digital circuits make it more difficult to maintain a high yield. Diagnosis is the procedure used when circuit verification fails. Determining the cause of the failure and finding the possible defect locations are included in diagnosis. In this thesis, a procedure of diagnosing multiple net-faults is proposed. Many previous studies on fault diagnosis mainly focused on single failures. However, considering the increasing complexity of current devices, multiple fault models may better reflect the real failures. Therefore, this thesis aims at using multiple fault models for diagnosis, though only the single fault simulation information is used. We utilize test patterns that have high diagnostic coverage for single stuck-at and single transition faults. Thus, we can expect a better distinguishablility between faults and hopefully better diagnosis can be achieved. We propose a candidate filtering system based on probabilistic counting criteria, which is different from previous methods that simply relied on strict matching criteria and simple matching count. The proposed candidate filtering system utilizes information on passing patterns as well as that on both erroneous and error-free primary outputs of failing patterns to construct a balanced ratio-count for each fault that could potentially exist in the faulty circuit. By using such ratio-count for each fault, we hope to have better chances of discovering those faults that have been reported detected only few times. In reality this would be the case with hard to detect faults. Fault candidates are then filtered by dropping those with counts lower than an empirically determined threshold.